1. Field of the Disclosure
The present disclosure generally relates to electronic devices and, more particularly, to a system and method to substantially eliminate standby leakage current due to row-column shorts in semiconductor memory chips.
2. Brief Description of Related Art
Memory devices are electronic devices that are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins or ball contacts 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (DQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, a chip select (CS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in an array of rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns, respectively, in the array in response to decoding an address provided on the address bus 17. Data to/from the memory cells 26 are then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit 32. The I/O circuit 32 may include a number of data output buffers or output drivers to receive the data bits from the memory cells 26 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O circuit 32 may also include various memory input buffers and control circuits that interact with the row and column decoders 28, 30, respectively, to select the memory cells for data read/write operations.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock (CLK) signal, a Chip Select (CS) signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a Write Enable (WE) signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 is a simplified architecture for a portion of the memory device 12 shown in FIG. 1. It is evident that complex circuit details and constituent architectural blocks in the memory chip 12 are omitted from FIG. 2 for the sake of clarity and ease of illustration. As shown in FIG. 2, a data storage or memory array may consist of a matrix of storage bits or memory cells 26 divided into a left memory array 34 and a right memory array 36. Each memory bit being exclusively referenced by a corresponding row and column address (that may be present on the address bus 17). Each row of memory cells may be called a “wordline” (WL), whereas each column of memory cells may be called a “digitline” (DL). Each memory bit or memory cell 26 may be connected to only one corresponding digitline and only one corresponding wordline. In FIG. 2, for ease of illustration, each memory array is shown with one wordline—the wordline 38 in the left array 34 and the wordline 40 in the right array 36. Similarly, each memory array is shown with two digitlines—the digitlines 42 and 44 in the left array 34 and the digitlines 46 and 48 in the right array 36. It is noted that the digitlines 44 and 48 are denoted as “DL*” to indicate the paired nature of the digitlines 42 and 44, and 46 and 48, as is known in the art.
In FIG. 2, two equilibration (EQ) circuits 50 and 52 are shown—each one connected to a corresponding pair of digitlines. Thus, the EQ circuit 50 performs equilibration of digitlines 42 and 44 to the DVC2 voltage level (=Vcc/2 V) before a memory cell access or data sensing operation begins as is known in the art. Similarly, the EQ circuit 52 equlibrates the paired digitlines 46 and 48 to the DVC2 voltage level. A sense amplifier circuit consisting of a pair of cross-coupled PMOS (p-channel metal oxide semiconductor) transistors 54 (P1), 56 (P2), and a pair of cross-coupled NMOS (n-channel MOS) transistors 58 (N1), 60 (N2), connected as depicted in FIG. 2, is shown placed between the four digitlines 42, 44, 46, and 48 and operating on them to perform the data sensing operation as is known in the art. The PMOS transistor pair P1-P2 may be called “Psense-amplifiers” and the NMOS transistor pair N1-N2 may be referred to as “Nsense-amplifiers.”
The Psense- and Nsense-amplifiers 54, 56, 58, 60 work together to detect the data signal voltage in a memory cell and drive the associated digitlines, accordingly to Vcc and ground. For example, in case of the digitlines 42 and 44, the Nsense-amplifiers 58, 60 may drive the low potential digitline (e.g., the digitline 44) to ground and the Psense-amplifiers 54, 56 may drive the high-potential digitline (e.g., the digitline 42) to Vcc. The operation of the sense amplifier circuit (consisting of transistor pairs P1-P2 and N1-N2) may be controlled by the ACT (activation) signal 61 and the RNL (Row Nsense Latch) signal 62 connected as shown in FIG. 2. For example, the Psense-amplifiers may be activated when the ACT signal is at Vcca level (Vcc voltage for the array) or “high”, whereas the Nsense-amplifiers are turned on when the RNL signal goes to logic zero or ground level.
Isolation (ISO) devices are also important during data storage and sensing operations. These devices are generally NMOS transistors placed between the array digitlines and the sense amplifiers. In FIG. 2, the isolation transistors 64-65 are placed and can control the connection between the digitlines 42 and 44 in the left memory array 34 and the P-N sense amplifier circuitry (consisting of transistor pairs P1-P2 and N1-N2 as noted above), whereas the isolation transistors 67-68 are placed to control the connection between the digitlines 46 and 48 in the right memory array 36 and the P-N sense amplifier circuitry (or P1-P2 and N1-N2 transistor pairs). In other words, if digitline nodes X1 and X2 (not shown) were added in the sense amplifier circuitry in FIG. 2 to correspond with the digitline pair DL-DL*, respectively, the isolation transistor 64 is placed between digitline 42 in the left array and the node X1 and the isolation transistor 67 is placed between the node X1 and the digitline 46 in the right array. Similarly, the isolation transistor 65 is placed between the digitline 44 and the node X2 and the isolation transistor 68 is placed between the node X2 and the digitline 48.
The isolation transistors may function to electrically isolate the two memory arrays 34, 36 so that whenever a wordline fires in one of the arrays, the digitline capacitance in that array is reduced because of the isolation of the other array. Further, the isolation transistors may provide resistance between the adjacent P or Nsense amplifier and the associated digitlines. This resistance may stabilize the sense amplifiers and speed up the data sensing operation by isolating the highly capacitive digitlines. In FIG. 2, the activation/deactivation of isolation transistors is shown controlled by the application of the ISOL signal 66 and the ISOR signal 69 to the corresponding gates of the isolation transistors. The ISOL signal 66 controls the isolation transistors 64-65 for the left array 34, whereas the ISOR signal 69 controls the isolation transistors 67-68 for the right array 36.
FIG. 3 illustrates the voltage levels of the ISOL 66 and ISOR 69 signals in FIG. 2 during row activation and row standby states. As is seen from FIG. 3, both the isolation signals—the ISOL signal 66 and ISOR signal 69—are held at Vccp level during a row precharge or standby state. However, in FIG. 3, the ISOL signal 66 is shown to be held at a ground potential (0V) when a row (e.g., WL 40) in the right array 36 is activated or fired for data access. The 0V level at the ISOL signal line 66 results in turning off of the isolation transistors 64-65, thereby allowing for isolation of digitlines X1-X2 (not shown, as discussed before) in the sense amplifier circuitry from those in the left array 34. The ISOR signal 69 is still maintained at the Vccp level during this right-array row activation period. As is known in the art, the Vccp voltage level is more than the memory chip's operating voltage level or the “Vcc” level by Vth (threshold voltage) of a MOS transistor (NMOS or PMOS).
It is known in the art that modern memory circuit designs employ a negative wordline voltage (VNWL) (not shown) to reduce the memory cell leakage current when the corresponding wordline is “off” or “inactive” and to also improve the memory cell refresh characteristics. In FIG. 2, a prior art scheme of maintaining digitlines and wordlines in a memory array in a standby state (e.g., a memory row precharged state) is illustrated via the exemplary voltages illustrated on certain lines. As shown in FIG. 2, during a standby state (i.e., when a row is not fired to commence a data access operation thereon), the ISOL line 66 and the ISOR line 69 are held at Vccp voltage level, the ACT signal line 61 is held at a ground potential (here, at 0V), and the RLNL signal 62 is maintained at the Vcc/2 or DVC2 voltage level. During the standby state, the wordlines (e.g., the wordline 38) are precharged to the VNWL level, which, in case of the embodiment in FIG. 2, is negative 0.3 V (−0.3V). However, the digitlines (e.g., the DL 42 and DL* 44) are precharged to the Vcc/2 (or DVC2) voltage level during the standby state. A wordline may be fired when a Vccp voltage level is applied at the wordline (WL signal).
Because the wordlines and digitlines are precharged to different potentials and because the precharge voltage levels VNWL and DVC2 are internally generated within a memory chip, a row-to-column short may result in a significantly higher standby current when the memory chip 12 is in an inactive or standby state. In FIG. 2, an exemplary short between the WL 38 and the DL 42 is illustrated by a dotted line 70. In the event of such row-to-column short, the precharged lines DL 42 and DL* 44 (precharged to DVC2 level) would be pulled down to the VNWL level (−0.3V) due to leakage current of the row-to-column short 70 through the ISO gates (e.g., the gates of ISO transistors 64-65), which are held at the Vccp level. Because the ACT signal is held at the ground level (0V) during the precharge and standby states, the negative level on the lines DL 42 and DL* 44 will turn on the PMOS transistors 54, 56 in the Psense-amplifiers, thereby establishing a leakage path (DC leakage current) from GND (ACT line 61) to VNWL line (not shown) via the PI and P2 transistors as illustrated by the arrows 55 in FIG. 2. This DC leakage current increases the Icc current (i.e., the current consumption from the supply voltage Vcc) in the memory standby state, thereby increasing power consumption in and performance degradation of the memory chip 12.
In one prior art method, an attempt is made to stop the DC current through the PMOS transistors P1 (54) and P2 (56) of the Psense amplifiers by driving the ACT signal 61 to the VNWL level (−0.3 V) during the standby state. Thus, the voltage on the ACT signal 61 is maintained at the same level (VNWL level) as the voltage on the wordline 38 during the wordline's precharged state. However, such a use of negative voltage on the ACT line 61 may require use of thick layers of gate oxides for the ACT driver transistors (not shown) and the PMOS sense amplifiers 54, 56. This would cause performance degradation with the same size of devices. Otherwise, to recover the performance, a larger circuit layout area may be required. Further, such negative level on the ACT signal 61 may require changing the connection of the bulk nodes (not shown) of the PMOS transistors 54, 56 from GND level to VNWL level and may also require changing the transistors (not shown) handling the EQ signals in the EQ circuit 50 from thin oxide-based configuration to a thick oxide-based configuration. The thick oxide-based configuration may cause degradation of EQ performance. Further, the negative level on the ACT signal 61 may require changing the “low” level of the EQ signal (not shown) from the GND (0V) level to the VNWL level to ensure that the ACT pull-down driver (not shown) remains off during the row activation state. Because the transistors (not shown) in the EQ circuit 50 have a very large gate capacitance, the power consumption of the VNWL line (not shown) would increase when the EQ signal is held at the VNWL level.
In another prior art method, a bleeder transistor (not shown) controlled by an EQ signal (not shown) is provided so that when a row-to-column short occurs, the bleeder gate is turned off by a signal from a fuse (not shown). Then, the leakage current from the EQ signal to the shorted WL's off level is removed. However, in this method, when the DL line (e.g., the DL line 42) goes down to the VNWL level due to the short on the WL 38 precharged to the negative voltage level VNWL, the shared ISO transistor (e.g., similar to the transistor 64 in FIG. 2) does not completely turn off, which results in additional leakage current in the Psense-amplifiers (e.g., the transistor P1 and P2 in FIG. 2). Thus, this prior art method still has a DC leakage current problem from the sense amplifier nodes (e.g., transistors P1 and P2 in FIG. 2) to the negative WL node (e.g., the WL 38) through the ISO gates (e.g., the gates of ISO transistors 64-65).
It is therefore desirable to devise a system and method to prevent the standby leakage current at the Psense-amplifier transistors due to row-to-column shorts in memory devices without modifying the sense amplifier layout in a memory chip or the layout configuration of isolation transistors in the memory chip.